Eugene Cohen

When the trap handler (MTVEC) resides at an address that returns a TLM error, the debugger will lose control of the session. Specifically we end up in a loop where...

When attaching the debugger it seems that two single-steps are required to actually single step the first instruction. Turning on verbose debug, the first single-step results in a memory read...

We need a way for a debugger to regain control while the core is in in WFI. The [RISC-V Debug Specification](https://github.com/riscv/riscv-debug-spec/releases) states in section 4.3: > If halt is requested...