Debugger loses control when trap vector fetch fails

[quic-egmc]

When the trap handler (MTVEC) resides at an address that returns a TLM error, the debugger will lose control of the session.

Specifically we end up in a loop where the vm detects the instruction fetch error and tries to enter the trap handler.

        if(fetch_ins(pc, data)!=iss::Ok){
            this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
            pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);

the trap handler sets a new value for the next PC which causes execution to loop endlessly attempting trap handling.

As execution goes, this seems reasonable. But for the debugger interface we need a way to interrupt execution to see the state of the processor when in this looping trap handler state.

For the debugger we expect:

1. When single-stepping the PC will advance to the trap handler address but not fetch the trap handler (yet)
2. When running the debugger needs to be able to break execution, showing a PC value of the trap handler

When the debugger attempts to disassemble around the PC at the trap handler address it will get TLM errors and handle these appropriately.