Johan Euphrosine

> Magic DRC Check > Significant rework required @jeffdi do we have a more granular view of the required work?

with #155 I still get the following violations on https://github.com/efabless/caravel_user_project example project: ``` {{STEP UPDATE}} Executing Check 2 of 4: Klayout FEOL Total # of DRC violations is 163740 Please...

@kareefardi looks that there are some `RESISTANCE` specified for the non-default `VIA` wiring: https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0/blob/main/tech/gf180mcu_5LM_1TM_9K_7t_tech.lef#L322 is this issue about also having value in the via `LAYER` definitions? https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0/blob/main/tech/gf180mcu_5LM_1TM_9K_7t_tech.lef#L95

@RTimothyEdwards @tspyrou @donn is that a hard blocker for the PDK to be usable with OpenLane?

@maliberty @tspyrou looking at the tech lef: It seems that there are some `RESISTANCE` value for the fixed `VIA` definitions: https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0/blob/1ebee70d934f91f6b289419a2c724d91e0d04895/tech/gf180mcu_5LM_1TM_9K_7t_tech.lef#L1069 Given that that dimentions seem to correspond to the...

@tspyrou is there a `setRC.tcl` equivalent for OpenLane? @RTimothyEdwards is https://github.com/RTimothyEdwards/open_pdks/issues/281 the right issue to follow to track the OpenRCX refinements?

@maliberty oh I see, so this would eventually come up from the `gf180mcu` open_pdks openlane config: https://github.com/RTimothyEdwards/open_pdks/blob/cc0029b45c68137aa21323912f50d2fc17eeea13/gf180mcu/openlane/config.tcl#L114

@RTimothyEdwards looking at your example in https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0/issues/24#issuecomment-1322390666 couldn't the "not(FUNCTIONAL)" `specify` block also be moved to the common base functional cell's verilog file (`and2/gf180mcu_fd_sc_mcu7t5v0__and2.v`), it currently looks like it is...

Looking at the current structure of the skywater-pdk https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd/tree/main/cells/and2, it looks a bit different from the example provided in https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0/issues/24#issuecomment-1322390666: - https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd/blob/main/cells/and2/sky130_fd_sc_hd__and2.v is just a proxy with conditional `include` statements...

Would https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0/pull/26 be an acceptable workaround while @RTimothyEdwards suggestions get implemented consistently across all repositories ? It only address the missing `_func` but should hopefully unblock gate level simulation (assuming...