Cho Moon

There are multiple issues here. One of them is RSZ journal save/restore. Since this doesn't preserve the exact order of all the transforms, it's hard to do 100% restoration to...

I see 2 removed buffers and 45 swapped pin instances. [INFO RSZ-0059] Removed 2 buffers. [INFO RSZ-0040] Inserted 18 buffers. [INFO RSZ-0041] Resized 19 instances. [INFO RSZ-0043] Swapped pins on...

I think you mean function RepairSetup::addWireAndBuffer(). Yes, if we had a distributed RC or a pie RC, we can compute Elmore delay using downstream cap. The code seems to be...

> We don't have such an option for find and the other displays (layout, inspector). @precisionmoon - you originally asked for this feature - do you need to have a...

This is an STA issue. We haven't even got to CTS step (4_1) yet. But the SDC seems a little strange: create_generated_clock -name clk_gated -source clk -combinational clkgate/Q Usually, clock...

Should we limit unused modules to arithmetic modules with some attribute?

https://github.com/The-OpenROAD-Project/OpenROAD/pull/7626 should take care of limiting unused modules to arithmetic ones only.

> Is there a metrics PR for this? ORFS PR https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/3703 is available. I added UpdateRules label.

We're looking into this. This is the clock tree immediately after CTS before repair_clock_nets. The clock period is 6500 ps and there are ~240K FF sinks and 123 macro pin...

I can reproduce the latency of ~1600 ps and skew ~310 ps with the testcase. ``` Clock clock 1594.44 source latency dcache/data/array_0_0_ext/R0_clk ^ -1278.74 target latency dcache/data/io_resp_0_0[69]$_DFF_P_/CLK ^ 10.00 clock...