Anthony Campos

Support $bits on typedef of a union

6

I see $bits is supported in certain contexts per https://verilator.org/guide/latest/languages.html#systemverilog-2005-ieee-1800-2005-support I assume $bits isn't supported in the context below? Can you attach an example that shows the issue? (Must be...

**Describe the bug** As indicated by https://terostechnology.github.io/terosHDLdoc/docs/documenter/verilog_elements#typedefs Typedef's should be detected. If that example struct is put in a SystemVerilog file, it doesn't get detected. i.e. //! AXI-4 Stream typedef...

**Describe the bug** If a parameter is of type structure and if it is the last parameter in the parameter list, when generating the documentation, the ports are lumped into...

AXIS Mux Missing first tvalid?

11

@alexforencich I ran stimulus (two AXI Stream interfaces) through the axis_mux.v module and it seems to be missing the tvalid on the first beat on the m_axis output. So, if...