Anthony Campos
Anthony Campos
If this is an issue with Verilator itself, I am not familiar with debugging this type of application, since I mainly work on FPGA's and code SystemVerilog.
@wsnyder anyone else willing to take this on?
@wsnyder Ok, please help clarify a few things and I'll try and tackle it. You mentioned "convert your test to test_regress format, and see it fail" --> What is the...
I'm also interested in this. Is it an alternative to the cli version? https://github.com/TerosTechnology/teroshdl-documenter-demo
@alexforencich The other issue I see is that if a change occurs on the select input, the first tdata of the next frame is still from s_axis[0] and not the...
I'm currently not using my interfaces's (aclk and arstn), I drive a clk, and rst into your axis_mux module. I agree with you on tready, but the s_axis[i].tready I'm driving...
Ok, I'm sure I would have noticed this by adding some formal properties to check the protocol, and with the mod to my own module, we would have caught it...
I think my use case for this axis mux is not applicable. I need to switch between two always active AXIS Streams (i..e no backpressure), but it's not necessarily a...
Ok, I'll try and modify on my end (my svlog version) to see if I can get the expected behavior. I first have to fix my stimulus generation. Thanks again...