Typedef's not interpreted by Documenter for SystemVerilog

[polyee13]

Describe the bug As indicated by https://terostechnology.github.io/terosHDLdoc/docs/documenter/verilog_elements#typedefs Typedef's should be detected. If that example struct is put in a SystemVerilog file, it doesn't get detected.

i.e. //! AXI-4 Stream typedef struct packed {
logic [7:0] data; logic [0:0] valid; logic [0:0] clk; } mystruct;

To Reproduce Copy and past above mystruct into a sv file. Declare a variable of that struct type as well.

Code `//! This is a multiline

//! entity description using MarkDown

module documenter_basic_example #( parameter PARAM1 = 1024 //! number of bytes in fifo )( //! description output port output reg [PARAM1-1:0] data, input clk, //! 300Mhz Clock input rstn //! other description );

localparam SN=11223344; //! SN for this node

//! Always example always @(posedge clk or negedge rstn) begin: myproc end

//! Instantiation example mymodule dut( .rstn (rstn), .clk (clk) );

//! Function example function reg[1:0] myfunc(input a,b); myfunc = {a,b}; endfunction

//! AXI-4 Stream typedef struct packed { logic [7:0] data; logic [0:0] valid; logic [0:0] clk; } mystruct;

mystruct struct1;

endmodule`

Please complete the following information:

• OS: Ubuntu 18.04
• VSCode version 1.82.2

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