Antoine Pitrou
Antoine Pitrou
> What is the use case, why do you want to know that after the benchmark? Because we're going to inject benchmark results in a database and then track results...
Ouch. Perhaps `xsimd_register`, in the case of SVE, can instead be a (pointer, length) pair or similar?
> The only problem I foresee is that `xsimd::batch` has `size` as a constexpr member, and I'm pretty sure that's incompatible with SVE. We can turn that into a method...
What would be the constraints exactly? If running on a 512-bit SVE CPU, would fixed-size 256-bit SVE be able to execute?
Also, in your example, can we not pass the bitsize directly instead of `__ARM_FEATURE_SVE_BITS`?
Uh, so let's hope most implementations choose the same register size then :-(
My question was whether one could write `__attribute__((arm_sve_vector_bits(128)))` directly without a specific compiler option. But apparently that doesn't work. ``` :4:50: error: 'arm_sve_vector_bits' is only supported when '-msve-vector-bits=' is specified...
Also one can't set any other value that the one given on the command line. Does `arm_sve_vector_bits` just only serve as a compile-time check that the right SVE width was...
@cyb70289 Sounds interesting! AFAIU, your approach requires setting the bit width at compile time?
(note that Travis-CI provides native Arm64 workers)