peijunh

mcon layer issue in Sky130 PDK causing no ap std::runtime_error

17

### Description Hello. I am using OpenLane to run my design. I use to way to determine the size of my design, one is to use the following config to...

ibex added to the design with drc lvs clean

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The Ibex RISC-V Core Wrapper instantiates an Ibex RV32 CPU Core, and wraps its data and instruction memory interfaces to TileLink Uncached Light (TL-UL). Now I add the ibex core...

Stuck at certain steps using caravel_user_project and caravel_user_project_analog.

1

Hello, I am using my design as macro, and I want to insert it into the caravel project. I tried both caravel_user_project and caravel_user_project_analog. Both of them get stuck at...

I am trying to use uhdm to synthesize a design that contains both verilog files and system verilog files. During synthesis, it reports this error: >/openLANE_flow/designs/opentitan_soc/src/ibex_cs_registers.v:1021: ERROR: Left hand side...