The-OpenROAD-Project
ibex added to the design with drc lvs clean
The Ibex RISC-V Core Wrapper instantiates an Ibex RV32 CPU Core, and wraps its data and instruction memory interfaces to TileLink Uncached Light (TL-UL). Now I add the ibex core to OpenLane. I run the whole OpenLane interactive flow without seeing drc, lvs error.
@donn this looks ok to me but I'll leave it to you to approve. How can we get it into the regression for OL?
We'd have to run the flow at least once and get the results then add them to SW_HD.csv.
Until that's done, I can't merge this…
@donn I have already run the flow. should I provide the resulted gds? or provide the log file?
We have the concept of a “run path” in OpenLane: under the design’s folder, there is runs.
Whatever the run that succeeded is, send me its folder.
The run file is large and cannot be attached directly even after compressing. So I upload it in my github and please go to there to git clone it. The name is ibex.tar.gz. Thanks git clone [email protected]:peijunh/vlsipool_tranfer.git
Sorry for the late reply.
Uh, neat results, but we’d have to also run on the various other SCLs and add the results to all those files… It’s quite laborious.
There probably should be a system in place to do exactly that though. So that’s something to discuss.