Bill Flynn

[WARNING STA-0201] should be error condition

1

Macro I/O mismatches are detected early, but do not cause failure until LVS checking. Seems like this is almost always a setup error. Related: are there plans to allow log...

PPC 32BE Software Build Errors

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I had to change a few minor things to get a software compile to complete for a PPC 32BE core. https://github.com/OpenPOWERFoundation/a2o/tree/master/dev/build/litex 1. meson failed with cpu family set to 'ppc'....

I often use the gtkwave ```Edit->Combine Down (F4)``` function to collect related signals (like valid+data) and then apply a process or transaction filter to the resulting vector. Did I miss...

Completions eventually get X's when FLOAT_TYPE = 0 (no FPU gen'd).

Can the 'entries' parameters be made to work? RTL doesn't compile when changed. ``` RV_FX0_ENTRIES 12 // and FX1, LQ, AXU0, AXU1, UCODE ```

Setting works at 16 but not 8 or 4. Are there other dependencies, like CPCRx values or RV settings? ``` `define CPL_Q_DEPTH 16 ```

These parameters do pass initial sim. Determine if ```IBUFF_DEPTH=4``` can/should be supported, and document. Also, prefetch enabled with different values should be tested. ``` `define IBUFF_DEPTH 6 //wtf 4 fails...

Sim fails on second ifetch. ``` `define INCLUDE_IERAT_BYPASS 0 // 0 => Removes IERAT Bypass logic, 1=> includes (power savings) ```

Setting DC size to 16K causes some vector size warnings, and fails sim (X's after ~1K cycles). ``` `ifdef DC_32 `define STQ_DATA_SIZE 64 // 64 or 128 Bit store data...

These settings compile/elab but hangs in sim (no completions). Need to document dependencies/requirements/etc. and test. ``` `define LDSTQ_ENTRIES 4 // ?order? `define LDSTQ_ENTRIES_ENC 2 `define STQ_ENTRIES 5 `define STQ_ENTRIES_ENC 3...