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enjoy-digital
PPC 32BE Software Build Errors
I had to change a few minor things to get a software compile to complete for a PPC 32BE core.
https://github.com/OpenPOWERFoundation/a2o/tree/master/dev/build/litex
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meson failed with cpu family set to 'ppc'. Changing it to 'powerpc' made it a warning only.
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comment this line in pythondata-software-picolibc/data/newlib/libc/machine/powerpc/setjmp.S
#error 32-bit -
remove extra parens in pythondata-software-picolibc/data/newlib/libc/include/machine/endian.h
#define htonl(_x) __htonl(_x)) #define htons(_x) __htons(_x)) #define ntohl(_x) __ntohl(_x)) #define ntohs(_x) __ntohs(_x))
I can build software and run on Verilator after a change to picolibc meson.build to set io_long_long = false. Looks like printf is having problems with %d but the core runs.
litex_term socket://localhost:2592
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Aug 21 2022 18:36:00
LiteX git sha1: 33ae301d
--=============== SoC ==================--
CPU: a2owb @ 10�MHz
BUS: WISHBONE 39-bit @ 4GiB
CSR: 39-bit data
ROM: 6�KiB
SRAM: 6�KiB
MAIN-RAM: 16��{KiB
--========== Initialization ============--
--============= Console ================--
litex> wtf
Command not found
litex>
I was also able to build the core as 64LE. Same printf problems but the core runs. I did have to set up the CSR translation to be big-endian.
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Aug 23 2022 10:29:40
LiteX git sha1: 33ae301d
--=============== SoC ==================--
CPU: a2o_WB_64LE @ 10�MHz
BUS: WISHBONE 39-bit @ 4GiB
CSR: 39-bit data
ROM: 6�KiB
SRAM: 6�KiB
MAIN-RAM: 16��{KiB
--========== Initialization ============--