[WARNING STA-0201] should be error condition

[openpowerwtf]

Macro I/O mismatches are detected early, but do not cause failure until LVS checking. Seems like this is almost always a setup error.

Related: are there plans to allow log messages to be altered by tcl (info/warning/error, possibly custom text, etc.)?

From intial floorplan log (Verilog macro wrapper does not match actual macro):

[WARNING STA-0201] /data/projects/toy-sram-mpw7/openlane/toysram/runs/22_09_19_16_21/results/synthesis/toysram_site.v line 4666, instance \ra_0.genblk1.ra  port rd_dat_0 not found.

[maliberty]

We did debate about user controls for error messages. We would never allow a downgrade (ie error to warning) but could consider allowing an upgrade. I have never seen custom text - how would that be used?

[openpowerwtf]

If I am not anywhere near tapeout stage (early development, experimenting, bug avoidance, etc.), downgrading messages to progress further could be useful. Presumably a final check would disallow any error bypassing or force a special writeoff.

I was thinking adding custom text might be useful to simplify post-processing of logs (like tagging sets of messages). Not a necessity but could be useful.

[maliberty]

You asssume that if you continue past an error the code will work correctly. In general it won't and it isn't a design expectation. If something can be continued after it should be a warning and not an error.

[vijayank88]

@maliberty Is that required further support?