cve2
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openhwgroup
The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
Note: this is an optional task. All other CORE-V cores have opted _not_ to do this, in favour of a task such as #223. This task is complete when a...
This task is complete when: - the [riscv-dv](https://github.com/chipsalliance/riscv-dv) random instruction stream generator is integrated into the UVM verification environment. - the [corev-dv](https://github.com/openhwgroup/core-v-verif/tree/cv32e40s/dev/cv32e40s/env/corev-dv#corev-dv) extension mechanism is in place for CV32E20. -...
This task is complete when: - all IBEX-specific content is either removed or deprecated. - all CSRs have been updated. - the RVFI implementation is fully documented. - Mike stops...
Currently, the CV32E20 UVM verification environment only exists on the [cv32e20/dev](https://github.com/openhwgroup/core-v-verif/tree/cv32e20/dev) branch of CORE-V-VERIF. This task is complete when cv32e20/dev is successfully merge to the [master](https://github.com/openhwgroup/core-v-verif/tree/master) branch.
This task is complete when: - the proper MISA value for CV32E20 is determined and captured in the User Manual. - the RTL is updated to match the UM. -...
As of 2023-12-30, the CORE-V-VERIF UVM environment supported the ImperasDV reference model. At this time none of the OpenHW Contributors to this project have access to an ImperasDV license, so...
This is a _nice-to-have_, not must-have, feature. Within CORE-V-VERIF there is a simple test-bench called the "core testbench" that can be run with Verilator. This testbench can only support simple...
The objective of the task is to run successfully cve2 and spike in tandem mode with a riscv-dv generated elf
Provide details on the implementation decisions to align both RTL and Reference Model. This is needed in order to do proper step-by-step comparisons
The objective of the task is to have a UVM environment capable of processing RISC-V instructions retired by the core. This is required to send the instructions to the subscribers...
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The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.