Create stand-alone RISCOF environment for the CV32E20

[DBees]

Note: this is an optional task. All other CORE-V cores have opted not to do this, in favour of a task such as #223.

This task is complete when a stand-alone RISCOF environment for the CV32E20 is in place and the Architectural Test-suite has successfully run. See cv32e40p-riscof for an example.