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UVM Sequence item for RISC-V instructions

Open DBees opened this issue 10 months ago • 0 comments

The objective of the task is to have a UVM environment capable of processing RISC-V instructions retired by the core. This is required to send the instructions to the subscribers in the UVM environment as coverage or Reference Model for step-by-step comparisons.

DBees avatar Apr 11 '24 23:04 DBees