cve2
cve2 copied to clipboard
The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
### Task Description CVE2 has some parameters to set the debug mode for example, while it should use an input signal (static) like the CVE4 ### Description of Done align...
### Bug Description The CVE2 documentation [read online at ReadTheDocs](https://docs.openhwgroup.org/projects/cve2-user-manual/en/latest/) at [cve2-user-manual/en/latest/internal](https://docs.openhwgroup.org/projects/cve2-user-manual/en/latest/02_user/integration.html) says that CVE2 should start at [boot_addr_i + 0x80] (https://docs.openhwgroup.org/projects/cve2-user-manual/en/latest/02_user/integration.html#interfaces) but I do not find any information on...
### Bug Description obi2ahbm_adapter.sv.. if byte access 24bits , bridge don't split 2 trans
### Task Description As reported in #263, this repository has an [examples/simple_system](https://github.com/openhwgroup/cve2/blob/1786fbfab7e0e2128fbf94495e9bd3c4896d526b/examples/simple_system/README.md?plain=1#L1) directory. Typically CORE-V core repositories do not include such examples as our members tend to have their own...
Improvements on the RVFI tracer to enable interrupt injection and correct CSRs comparison
This task is complete when the development team agrees on the specific GCC or LLVM toolchain to be used for CV32E20 simulation verification. It is expected to be one of...
This task is complete when the checklist for the TRL-5 release of the CV32E20 is created and reviewed. Note that this task only refers to the definition of the checklist,...
This task is completed when all test-programs in [cv32e20/tests/programs/custom](https://github.com/openhwgroup/core-v-verif/tree/cv32e20/dev/cv32e20/tests/programs/custom) are running (not necessarily all passing).