Olof Kindgren

Ok, this is an interesting feature and I'm definitely open to adding more metadata to the EDAM file. I just want to be careful to not expose too much internal...

I tested this just now and there is actually a test that breaks with this change. test_capi2_get_files in `https://github.com/olofk/fusesoc/blob/main/tests/test_capi2.py` breaks. Also, I think you should convert the Vlnv object to...

@nopeslide I'm planning to release FuseSoC 2.0 very soon. If we want this patch to go in before that, then we need to fix the failing test and do the...

The behaviour of trying to program the FPGA is indeed a bit problematic and inconsistent between different backends and has been bugging me for a long time (see e.g. here...

FuseSoC 1.12 is only compatible with older versions of Edalize. It would be great if we could get FuseSoC 2.2 packaged instead but I'm not sure who to contact about...

Yes, some kind of protection is apparently needed. And if I understand correcty the fix needs to bee on the FuseSoC side. Patches welcome!

I'm not sure myself if it should be considered a bug or a feature. It is definitely asymmetrical but it was done for a reason. My thinking was that if...

Yes. #610 applied now. Can we close this?

The status is good. We have ulx3s in the list which has a similar FPGA as OrangeCrab. No one has added a target specifically for OrangeCrab though

Yes, this is a weakness with FuseSoC. It is something I hope to fix next year though. Working on a roadmap so it's easier for everyone to see