Olof Kindgren

My take on this is that it is quite useful (and common) to have illegal default values in cases that don't really have a sensible default, since Verilog requires a...

SERV doesn't have a debug interface, so it will not be able to communicate with a debugger at runtime. Regarding the first include, `system_timer.h` belongs to Zephyr, so if you...

@gatecat did a synthesis test of SERV for ASAP7 about two years ago (see this video around 3:00 https://award-winning.me/serv-for-a-fistful-of-gates/) which indicated it was around 94um2. Note that this is excluding...

I see. To clarify, I didn't really mean using all of subservient, but perhaps the inner layer (subservient_core) if you want to use a combined memory for RF and code+data....

It sounds like a really cool project btw :)

Sorry for being a bit slow here. Looking at the code I wonder if we need the `-p` switch at all. That would be required to create parent directories, but...

It does seem to work with newer versions in practice, despite the strict version check. In order to run riscof with SERV I'm using a forked version of riscv-config where...

Include directives shouldn't be a problem as we can mark the RDL files that need to be included with `is_include_file : true` in FuseSoC. Agree that multi-file compilation is to...

Good question. I have never really understood how the logging module really works. Many of the modules have this line `logger = logging.getLogger(__name__)` in it. Does that make any difference?

I looked into the logs and it turns out @benreynwar did it with f4fad9131dabefedf830b40ecb3dfc6687131d86 back in 2017. Any clues, Ben? :)