Olof Kindgren

> > Then I would like to talk about the chipdb files. I have a memory those were discussed last time we looked at nextpnr-xilinx, but can't find that discussion...

> FYI - https://github.com/hdl/constraints Yes! That's likely the best source for this kind of data and I would highly recommend adding to that over keeping a separate board database. Still...

Sorry for the delay. Haven't been much near a computer lately. So, I think the best plan of attack is still to first plug in the individual tool classes, followed...

> > Then the question still remain about the chipdb files. I _really_ think nextpnr-xilinx should be able to figure this out by itself, or at least query the system...

> > Looking ahead, I think the `split_io` option needs to go. It looks like a list of options, but looking at the code, the four first elements are hard-coded...

> > Thinking about it again now I think perhaps we should choose another route and add in the split_io script and the extra yosys invocation in flows/f4pga.py instead since...

We have come full circle. I was just looking at @Pocketkid2's propsed changes to yosys regarding split_io and was wondering if my tcl/python cleanup patch (https://github.com/SymbiFlow/f4pga-arch-defs/pull/2371) was merged, when I...

Hi @jgbhatia. Thank you for this patch. I'm not completely sure how the spyglass backend works but if I understand correctly it tries to run multiple goals and if any...

I see. I have no idea why `set_option enable_pass_exit_codes yes` is in the template file. Generally, I want to avoid setting default options for exactly this reasons. Different people have...

@mithro My ambition is to support both use cases. People with virtual hardware or vtr devs will likely know where they have their architecture files. This is fine. We just...