Alex Martens

Small update on this, the `ip_in_core` feature is available on nightly, and I added support for it in #245. I opened a PR to add `ip_in_core` support to `embedded-nal`: https://github.com/rust-embedded-community/embedded-nal/pull/81

I've been thinking about this for a bit and can't think of any reason for this, but can't come up with any ideas. I haven't seen anything like this myself...

That's good information! Do you know if it is reproducible with `opt-level = "s"`? I will have to check, but I think that's what most of my projects have been...

I really appreciate the reproduction! I don't have a lot of time these days, but I'll try to investigate this weekend!

It has been a while, but I finally got around to trying to reproduce this, but have not been able to yet :( Here's my full code: https://github.com/newAM/w5500-issue-252

:facepalm: that was it! I can easily reproduce it now, thanks! I captured the SPI bus with my LA, here's the working (`opt-level=1`) case (data from 10.0.0.3):  and here's...

I'm pretty sure this is some SPI bus timing being violated when the code is optimized better. It is always 0x40, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00 when the...

A bit of digging I found an example waveform of this on my LA. TCS here is 20ns, lower than the 30ns minimum. Also it gets asserted before SCLK is...

This seems to make everything work at all opt-levels. ```diff diff --git a/ll/src/eh0/vdm.rs b/ll/src/eh0/vdm.rs index d43cf79..8c3287f 100644 --- a/ll/src/eh0/vdm.rs +++ b/ll/src/eh0/vdm.rs @@ -96,6 +96,7 @@ where self.cs.set_low().map_err(Error::Pin)?; let result =...

async interrupts are easy enough with the embedded-hal-async abstraction for GPIOs. Aside from that not much has been done since this PR, other projects have been taking my time away...