nblei
nblei
**Summary** Currently, a `unique case` statement without a `default` case results in a linter warning to `Explicitly define a default case for every case statement.` However, the `unique case` statement...
### Server name veridian ### Server homepage https://github.com/vivekmalneedi/veridian ### Languages SystemVerilog ### Is this server added in lspconfig? - [ ] Yes - [X] No ### How is this server...
I need to modify gate level netlists by changing the input and output of individual gates. Currently, I'm doing this using PCRE. This is an inelegant and haphazard solution. I'd...
A number of bugs exist in the sample code which cause runtime errors (segfault on my system). The first is that `CBFormat myFormat` must be configured. I used `myBFormat.Configure(1, true,...
Currently veryl's enums map directly to SV enums. However, Rust's enums are far more powerful and would map closer to SV's tagged unions. However, tagged unions are basically never supported...
Consider the common use case where the value carried on a bus is only relevant if a flag is set. For example, the value of `wdata` to a memory is...
Dalance, Not sure if there's interest, but a nice feature may be emitting SystemVerilog with back annotations of some sort. While this would help humans who are performing verification to...
Dalance, I would like to add a type checking pass which has a primary goal of evaluating the size (in bits) and packedness of each datatype. The way I see...
Modern standard cell libraries include flops with asynchronous sets. For example, DC maps ``` module f( input clk_i, input rst_ni, input set_i, input q_i, output reg q_o ); always_ff @(posedge...
Hey Dalance, what do you think of the idea of doing a tutorial or workshop at ASPLOS (https://www.asplos-conference.org/asplos2024/cfp/) or similar architecture / EDA conference? Personally I think Veryl has the...