[Feature] Support for asynchronous set signal

[nblei]

Modern standard cell libraries include flops with asynchronous sets. For example, DC maps

module f(
    input clk_i,
    input rst_ni,
    input set_i,
    input q_i,
    output reg q_o
);

always_ff @(posedge clk_i or negedge rst_ni or negedge set_i)
    if (!rst_ni) q_o <= 1'b0;
    else if (!set_i) q_o <= 1'b1;
    else q_o <= q_i;

endmodule

to

module f ( clk_i, rst_ni, set_i, q_i, q_o );
  input clk_i, rst_ni, set_i, q_i;
  output q_o;

  // I have redacted the specific register name to avoid any NDA violations
  reg_type1 q_o_reg ( .d(q_i), .clk(clk_i), .rb(rst_ni), .psb(set_i), 
        .o(q_o) );
endmodule

And removing the reset signal from the verilog, we get

module counter ( clk_i, rst_ni, set_i, q_i, q_o );
  input clk_i, rst_ni, set_i, q_i;
  output q_o;

  reg_type_2 q_o_reg ( .d(q_i), .clk(clk_i), .psb(set_i), .o(q_o) );
endmodule

Thus, Veryl needs to support a set signal in always_ff declarations. I propose the following:

1: Redefine the AlwaysFfDeclaration to have two optional AlwaysFfSetReset non-terminals (which is just a renamed AlwaysFfReset.

AlwaysFfDeclaration: AlwaysFf LParen AlwaysFfClock [Comma AlwaysFfSetReset] [Comma AlwaysFfSetReset] RParen LBrace { Statement } RBrace;

2: Assume that if two AlwaysFfSetReset non-terminals are present, then the order is set then reset (largely because 'set-reset' sounds better in english than 'reset-set').

3: Add a IfSetStatement statement.

4: While flip-flops typically prioritize reset > set, it is easy enough to prioritize set > reset with two inverters. Thus, let the user specify their intended priority based on the order of the IfSetStatement and IfResetStatement statements.

Veryl is feature incomplete if it cannot handle asynchronous set flip-flops.