nblei

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The veridian project (https://github.com/vivekmalneedi/veridian) has a yaml format for this purpose.

I think I may be having a related issue. Namely, `instr_req_o` is set when there is a branch, even if the branch target is cached, resulting in extraneous instruction memory...

OK. I think why I'm seeing an (unnecessary) delay is because I do not have the instruction memory respond with `instr_gnt_i` until the access has been nearly completed (a cycle...