Mehdi Saligane

padding on DECAPs creates overlap error with tapcells

6

`Summary` While running the temperature sensor design, I got a new error related to how padding is used. Padding seems to be applied to `sky130_fd_sc_hd__decap_4` cell and the tool thinks...

## Expected Behavior The expected syntax / terminology should be as follows: ``` .SUBCKT sky130_fd_sc_hs__decap_4 VGND VNB VPB VPWR *.PININFO VGND:I VNB:I VPB:I VPWR:I MI2 VPWR VGND VPB pfet_01v8_hvt m=1...

Encountered unhandled typespec in process_parameter

1

This is issue might be related to: #518 When reading multiple sv files and running through synthesis in [openlane](https://github.com/msaligane/openlane/tree/use-yosys-uhdm-plugin/designs/opentitan_soc). I get the following error message: ``` 23. Executing Verilog with...

error when reading multiple sv files

1

If I use [this] (https://github.com/msaligane/openlane/blob/543cae952326d1b2dd9441f9bcf16ab4d6719e44/designs/opentitan_soc/config.tcl#L5) Inside the `config.tcl` ([example](https://github.com/msaligane/openlane/blob/use-yosys-uhdm-plugin/designs/opentitan_soc/config.tcl)) : ` ```“set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.sv]”,``` yosys will return an error saying that it cannot read the sv files. it should...

m4.pd.1d density check

4

Hi! We are trying to close our submission (precheck is clean) however, the tapeout step (metal fill) is failing and gives the following error:  Unfortunately, I can only check...