Encountered unhandled typespec in process_parameter

[msaligane]

This is issue might be related to: #518

When reading multiple sv files and running through synthesis in openlane. I get the following error message:

23. Executing Verilog with UHDM frontend.
ERROR: /openLANE_flow/designs/opentitan_soc/src/ibex_core.sv:22: Encountered unhandled typespec in process_parameter: 'rv32m_e' of type 'unsupported_typespec'

You can replicate this issue by cloning this fork of antmicro's and running: ./flow.tcl -design opentitan_soc

[kamilrakoczy]

Surelog/UHDM requires that all files required for a design to be parsed together, so reading them separately is wrong and causes yosys to do not recognize modules defined in other sv files.

More information how to read multiple files together is in https://github.com/chipsalliance/UHDM-integration-tests/issues/518, please confirm, that this fix helped.