error when reading multiple sv files

[msaligane]

If I use [this] (https://github.com/msaligane/openlane/blob/543cae952326d1b2dd9441f9bcf16ab4d6719e44/designs/opentitan_soc/config.tcl#L5) Inside the config.tcl (example) : ` “set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.sv]”,

yosys will return an error saying that it cannot read the sv files. it should be expected to read multiple files without having to list them all like here.

Additionally, to work around that, I had to hack the openlane synth.tcl script by adding the following line (which isn't great) from: read_verilog_with_uhdm -parse -sverilog $::env(VERILOG_FILES) to

foreach file $::env(VERILOG_FILES) {
        read_verilog_with_uhdm -parse -sverilog $file
}

Doing so, yosys will not be able to recognize modules defined in other sv files.

[kamilrakoczy]

I prepared fix for this: https://github.com/antmicro/openlane/commit/1185510efbe8d2a7dd1e30ac6bd77808c98dd3d7

It turned out, that tcl were passing all found files with glob as a single argument, instead of multiple. This fixes this problem and expands variables in-place before evaluating.

Note: Surelog/UHDM requires that input files to be parsed in order of usage. This means, that if some file is using typedef/parameter from another file (for example package), that file needs to be parsed after package file. Using glob to get list of files can (and probably will) break this order.