Max Korbel
Max Korbel
### Motivation Sometimes there's a bunch of different independent hierarchies that we want to generate SystemVerilog for. If we generate them with independent `SynthBuilder`s, then any shared sub-modules may be...
### Motivation When you add a sub-interface to a `PairInterface`, then if you ever use `receiveAll` or `driveAll`, it won't apply to all the `subInterfaces`. It would be nice if...
### Motivation The option to expose `modify` is up to the constructor of an interface extending `PairInterface`, but at the time of adding a sub-interface is likely a point where...
### Motivation A lot of the time, someone may want to instantiate a SystemVerilog module without creating a new class definition or defining any internal behaviors. In these cases, you...
The documentation for instantiating other things in SystemVerilog is not clear enough and could really use some examples. https://intel.github.io/rohd-website/docs/external-modules/ It would be nice to cover: - `ExternalSystemVerilogModule` - `CustomSystemVerilog` -...
### Motivation Much of the time, only signals that are actively being listened to or outputs of a module are the only things that matter for an accurate functional simulation....
### Motivation Sometimes it would be nice to be able to transpose an array. There may be other utilities as well worth adding. ### Desired solution Add utilities like transpose...
## Description & Motivation Updating to use a new type of self-hosted runner for GitHub actions. This should help with the slow pick-up of jobs from the GitHub-hosted runners. This...
### Motivation In addition to #69, it would be nice to be able to use an async reset on the flop. ### Desired solution Add a way to configure the...
### Motivation The `ReadyValidPipeline` currently hijacks access to `stall` signals. This is annoying if you want to stall pipeline stages for other purposes than just backpressure on the end of...