Max Korbel

### Describe the bug This assertion exists in `interface.dart` in `Interface._setPort`: ```dart assert(!_ports.containsKey(portName), 'Port named $portName already exists on this interface.'); ``` This should be an `Exception`, not an `assert`....

### Motivation There are some cases where the top of the module definition may need to be modified slightly, but not entirely. For example, adding package imports (in case they...

### Motivation There are scenarios where it's convenient to use a `List`, especially as an argument to functions or constructors for modules. Keeping it as a `List` requires iterating through...

### Motivation There are some things in ROHD that can be a bit verbose/redundant. For example, a simple port whose variable name and String port name are the same, and...

### Motivation In SystemVerilog and some other HDLs/generator frameworks (e.g. Chisel) there are APIs for assigning an element/range of a bus/array where the index is itself a signal. This implies...

### Motivation The "port" style constructors include: ``` Logic --> Port LogicArray --> LogicArray.port LogicNet --> LogicNet.port LogicArray.net --> LogicArray.netPort ``` One of these is not like the others. Moving...

### Motivation Often there is a "default" value that would be desirable for most states in a `FiniteStateMachine`, but the current implementation requires repeating the same default across all states...

### Motivation There are multiple places across ROHD and ROHD-HCL where public and private implementations of some common math operations are included. For example: - `LogicValue` has `clog2` - `FiniteStateMachine`...