Max Korbel

### Motivation There are a variety of ways to have optional output ports, for example: - A bool to control whether it gets generated with a nullable getter - An...

Optimize `Sum` and `Counter` to avoid underflow/overflow logic when possible

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### Motivation As a follow-on to #89 It should be possible to avoid creating logic which considers whether an overflow/underflow has occurred by determining whether it is *ever* possible. For...

### Describe the bug If `Simulator.run` throws an exception, the `Test` should immediately end (and fail). However, as currently implemented in `start`, it can cause a hang instead. Depends on...

### Motivation `Cosim` modules currently have the ability to specify things like simulation and compile time arguments. Sometimes, it might be useful to provide compile, simulation, or other arguments at...

There is a block of code in rohd_connector.py which is designed to detect whether there was a timeout waiting for the SystemVerilog simulator to complete a tick: ```python if not...

There may be scenarios where a user of the RohdConnector would want to know whether it had previously encountered some error in post-simulation routines. An indication other than an exception...

A `#` delay in the SystemVerilog simulator can result in signals changing at intermediate times between ticks and not edge triggered by any signal driven by ROHD Cosim. We should...

The `throwOnUnexpectedEnd` scenarios are under-tested for `PortConfig`.

We have existing tests with `PortConfig` for scenarios where errors occur during the simulation, but we should make sure simulations gracefully end even if the crash occurs before `Simulator.run` is...

The ROHD bug https://github.com/intel/rohd/issues/253 is preventing us from doing an `await` on `Simulator.reset()` in finish_test.dart because the simulation doesn't get marked as ended, which the reset will wait for. Once...