Max Korbel

Add a switch to disable synthesizer collapsing functions

1

## Motivation Sometimes users who are interested in the readability of generated SystemVerilog or ROHD developers are curious about how in-line modules and assignment collapsing are performed to create the...

Support tagging of generated SystemVerilog `begin` and `end`

1

## Motivation Some users have extra preferences about the readability of generated SystemVerilog for their applications. It would be nice to use the tagging mechanism for if, case, etc. in...

A way to group blocks of generated output

1

## Motivation Some users are particularly interested in the organization of generated output code. Within a single module, there can be a desire to group together certain logic in the...

Mechanism to warn about integer truncation in constants

2

## Motivation Sometimes one might want to create a `Const` which requires passing an integer, but the integer doesn't "fit" in the specified width of the constant signal. The current...

Add support for `++` and `--` types of operations in conditional logic

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## Motivation There are cases in procedural execution in `_Always` blocks where `++` and `--` are useful. Dart does not allow overloading these operators, however. ## Desired solution Some sort...

Add `gt` and `gte` for consistency to `Logic`

1

## Motivation For equality, less than, and less than or equal to, `Logic` has `eq`, `lt`, and `lte`, respectively, since those operators have different meanings (object equality, conditional assignment, and...

## Motivation There are a variety of ways to create `Const`s to represent enumerable types in hardware with ROHD, and currently everyone comes up with their own way that's convenient...

Put Dumper into a separate isolate to avoid simulation slow-down

1

File operations might be a significant source of slowdown when running a simulation.

## Describe the bug It is possible to specify a `definitionName` that is not sanitary (as sanitized by `Sanitizer`), which means you can generate invalid SystemVerilog. ## To Reproduce Define...

Allow negative indices on `Logic` and `LogicValue` to relative to the end

1

## Motivation Python allows you to access the end of a list using negative numbers, which is a nifty feature. ## Desired solution Functions like `operator []`, `getRange`, and `slice`...