Tim 'mithro' Ansell
Tim 'mithro' Ansell
https://github.com/xobs/foboot/blob/0c6e44478963cd67b096d0d27976c43bfefcd216/hw/foboot-bitstream.py#L208-L218 ```python def __init__(self, toolchain="icestorm"): LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, toolchain="icestorm") # Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command. # The "-reult" adds an additional LUT pass to pack more...
``` (LX P=icebreaker.minimal F=stub R=master-lbe) tansell@tansell:~/github/timvideos/litex-buildenv$ make firmware-connect flterm --port= --speed=115200 [FLTERM] Starting... Unable to open serial port: No such file or directory ```
As @xobs pointed out in #109 the [Using](https://github.com/timvideos/litex-buildenv/wiki/Using) section of the wiki should also probably be in the README file.
It fails with; ``` tinyprog: error: unrecognized arguments: --program-image build/tinyfpga_bx_base_lm32.minimal//image-gateware+bios+none.bin ``` Should it be onstall from git rather than PyPi?
``` The following builds succeeded ============================================= arty base lm32 arty base or1k arty base picorv32 arty base vexriscv arty net lm32 arty net or1k arty net picorv32 arty net vexriscv...
``` - make firmware check (arty bridge_net lm32 firmware) [0/9315] --------------------------------------------- mkdir -p build/arty_bridge_net_lm32/ time python -u ./make.py --platform=arty --target=bridge_net --cpu-type=lm32 --iprange=192.168.100 --no-compile-gateware \ 2>&1 | tee -a build/arty_bridge_net_lm32//output.20181004-000927.log; (exit...
``` class Platform(XilinxPlatform): def __init__(self, toolchain="vivado", programmer="vivado", device="xc7a35t", build_multiboot=True): XilinxPlatform.__init__(self, "{}-fgg484-2".format(device), _io, toolchain=toolchain) self.sysid = 0x4b01 self.toolchain.bitstream_commands = [ "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", "set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1...
There is a huge amount of duplication between the various targets. For example the [base.py of the Atlys](https://github.com/timvideos/litex-buildenv/blob/master/targets/atlys/base.py) is almost identical to the [Opsis base.py](https://github.com/timvideos/litex-buildenv/blob/master/targets/opsis/base.py). As we are about to...
There are a *bunch* of scripts which are suppose to download the prebuilt firmware, gateware, headers, etc. They are; * https://github.com/timvideos/litex-buildenv/blob/master/scripts/download-prebuilt.sh * https://github.com/timvideos/qemu-litex/blob/master/build-litex-qemu.sh * https://github.com/fupy/micropython/blob/master/ports/fupy/get-gateware.sh It would be nice if...