Tim 'mithro' Ansell
Tim 'mithro' Ansell
[bazel is Google's build system](https://bazel.build/). Currently it primarily targets things like C++ and Java server building, but it would be nice if it had strong support for interfacing to HDL...
Verilog to Routing supports using Quartus as a frontend for synthesis and then VtR for doing the place and route. You can find out more about this flow @ http://www.eecg.utoronto.ca/~kmurray/titan/fpl_13_demo.pdf...
I suggest; > Python Library for interacting with EDA tools. Currently you take like 5 paragraphs to describe EDAlize and I get bored before actually knowing what it does....
See https://github.com/m-labs/migen/issues/153
@SiFive and @drom have created a thing called [DUH](https://github.com/sifive/duh). This format describes things like wishbone busses and stuff. This seems like a good thing to integrate with FuseSoC. It would...
https://numato.com/product-category/fpga-accelerated-computing/expansion-modules
Haven't had a chance to see if you have already included all my stuff or not. Take a look at https://github.com/mithro?utf8=%E2%9C%93&tab=repositories&q=Pmod&type=&language=
https://github.com/mithro/kicad-pmod
I have a spreadsheet at https://docs.google.com/spreadsheets/d/1D-GboyrP57VVpejQzEm0P1WEORo1LAIt92hk1bZGEoo/edit Important for HDMI and other speed high speed designs.
They need to be indented more.