Tim 'mithro' Ansell
Tim 'mithro' Ansell
My understanding is that asserting `csr.we` should cause the storage to get the contents from `csr.dat_w`. This doesn't seem to be happening during simulation. I also found the following; https://github.com/m-labs/misoc/blob/57ebe119d80beabad30d232fc3c9229882042807/misoc/cores/spi2.py#L496-L497
* Bunch of small changes to the Makefile (enabling debug symbols and fixing the dependencies for the bios). * Fixing the or1k exception stack. This fixes the issues with the...
As far as I can tell, migen.actorlib is no longer a thing? https://github.com/m-labs/misoc/blob/master/misoc/cores/framebuffer/format.py#L6
It would be nice to have a "spi settings" thing for different SPI flash chips following the same vian at https://github.com/m-labs/misoc/blob/master/misoc/cores/sdram_settings.py#L60 for the SDRAM ICs.
I forgot to init the submodules when cloning misoc. Running `python setup.py install` worked fine but I later got an error like the following when trying to build; ``` CC...
`'\r\n'` works "out the box" with a lot more serial terminal programs (minicom, putty, etc).
So I saw in #3 that you are looking at trying to keep hdlparse simple and targeted at just being used for documentation generation. > In the IEEE Verilog 1364-2001...
It is my understanding that this form of Yosys is no longer needed as everything has been merged upstream or moved into yosys-symbiflow-plugins. We should thus cleanup this repository and...
### Why did we need this? (what does this change enable us to do) Enables Verilog attributes to be used on parameters. ### What did it change? The Yosys RTIL...
### Why did we need this? (what does this change enable us to do) VPR uses a different model for how the CARRY4 works. This is needed because "chain" pack...