Tim 'mithro' Ansell

Rate limit exceeded with no more information

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### Description Currently trying to install tools and getting the following error; ``` ./venv/bin/volare enable --pdk sky130 Version cd1748bb197f9b7af62a54507de6624e30363943 not found locally, attempting to download… Failed to obtain cd1748bb197f9b7af62a54507de6624e30363943 remotely:...

License check not suitable

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(Plus, the current functionality is wrong.) The tool should basically check for compliance with the stuff described at https://opensource.google/docs/releasing/preparing/ with an extra requirement to have SPDX identifiers in files. There...

Generated macros uses analytical model rather than spice simulation

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For some reason these macros were generated with the analytical model meaning that timing data and fmax in the datasheets is mostly garbage. These macros should be generated with proper...

Set up readthedocs pull request rendering

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## Expected Behavior Sending a pull request on this repository shows how it will affect the documentation around the standard cells found at https://gf180mcu-pdk.rtfd.io This could be done by setting...

## Expected Behavior The fill schematic is rendered correctly or manually overridden to make sense. ## Actual Behavior Fill appears to be rendered as some giant line? https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0/blob/69e8c5b9c2e105a46b78bed8b2236947ee30e338/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill.schematic.svg See https://raw.githubusercontent.com/google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0/69e8c5b9c2e105a46b78bed8b2236947ee30e338/cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill.schematic.svg

## Expected Behavior Flip flop schematic rendering should look more like this;  This is likely because Yosys can't pull part or otherwise understand the `UDP` (user defined primitive) is...

## Actual Behavior Currently most of the buffers are getting rendered as an empty line as below;  ## Expected Behavior The buffer should be rendered more like this inverter;...

Each of the standard cell should have a Verilog test bench which tests the functionality.

CI on this repository should verify that the standard cells pass the GF180MCU DRC rules. Example GitHub Action at https://github.com/google/skywater-pdk-actions/tree/main/run-drc-for-cell-gds-using-magic

Add Atlys Board

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Pretty please :-P It should already be supported by FuseSoC right?