Tim 'mithro' Ansell

icon indicating a website link https://blog.mithis.net/

icon company @wafer-space icon location Sunnyvale, US icon location Founder and Leader of @timvideos

Results 1504 comments of Tim 'mithro' Ansell

Documentation check not suitable

@agorararmard -- Manual testing is testing that does not exist. Please set up testing so it can be run by any developer and by the CI system.

Technology LEF files have incorrect CPERSQDIST

Given that the proprietary tools ignore these values, I think we should remove them from the LEF files.

Technology LEF files have incorrect CPERSQDIST

Or set them to a known constant that is clearly a dummy / invalid value.

cells: rename functional module

@urish - I assume it is related to https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0/pull/27 ?

cells: rename functional module

@urish - Maybe your test could be added to the repository as a way to verify that the Verilog is working?

cells: rename functional module

Maybe? We are making up this as we go.

Set up readthedocs pull request rendering

@proppy - I believe this has been done?

Gate level verilog modules are horribly broken and unusable

@mkkassem - Can you please look at this with high priority and figure out the pathway forward?

Gate level verilog modules are horribly broken and unusable

@RTimothyEdwards - that sounds good to me!

Gate level verilog modules are horribly broken and unusable

I've previously tried to describe some of this in the doc at https://bit.ly/open-source-pdks-naming (specifically the [Recommended Verilog Include Structure](https://docs.google.com/document/d/1rDN5jw8sh0aTwf1jScn0nP2zy4FWLxC-82M8TL3Lbr4/edit#heading=h.m52rppi8kyfl) section).