mattfel1

For example, in BigIPZynq, ``` def divide(dividend: UInt, divisor: UInt, latency: Int, flow: Bool): UInt = { getConst(divisor) match { case Some(bigNum) => Utils.getRetimed(dividend / bigNum.U, latency, flow) case None...

Look-Through RegReads in Access Analyzer

7

See KMP. Looking into this now to see if its something stupid

Conflicting Port Connections

3

Try MD_Grid. Haven't looked into this at all yet but chisel crashes because of this

Loop Perfecter

4

In cases like ``` Foreach(...){i => mem(i) = Reduce(Reg[Int])(...){...}{...} } ``` We get an outer Foreach with a Reduce stage and a Unit pipe for the sram store. We can...

Fix buffering logic for more exotic cases

1

If there's a producer-consumer chain within a metapipeline, either: a. the space of the write, assuming iterators at and above the pipeline are constant, is the ENTIRE space of the...

May be worth having buffered DRAMs for large NNs with pipelined layers. App below is a good test ``` @test class DRAMBuffer extends SpatialTest { override def runtimeArgs: Args =...

Currently this is written as: ``` /** On-chip GEMM */ Stream.Foreach(M par MP, N par NP){(i,j) val prod = Reduce(Reg[T])(K by 1 par KP){k => getA(i,k) * getB(k,j) }{_+_}) val...

Reg Reset Handling

1

If someone writes this: ``` Foreach(...){i => val r = Reg[Int](5) r.reset r := ... ... := r } ``` In old spatial at least, the reset doesn't get handled...

API for unbiased and saturating casting

1

I added nodes and chisel backends for saturating ops by enclosing them in (like ``) and unbiased rounding by appending & (like `*&`) but I think there can be times...