Fix buffering logic for more exotic cases

[mattfel1]

If there's a producer-consumer chain within a metapipeline, either: a. the space of the write, assuming iterators at and above the pipeline are constant, is the ENTIRE space of the memory b. the space of the write always fully contains the space of subsequent consumer stages

Otherwise, buffering will result in incoherent copies across consumer iterations This is trivially true for registers of course, since the write is always over the entire space Furthermore, if a read occurs before a reaching write in a pipeline, that's almost trivially un-pipelinable (maximum initiation interval)

See MatMult_hierarchy tileC, the only known place where this bug occurs

[dkoeplin]

From discussion with Matt: Based on the access ranges, we see that the read occurs before the write, but the read never uses a result of that within the buffer. Hence this isn't actually a produce-consumer relationship, and the memory shouldn't actually be buffered at all. Previously we happened to be getting lucky by keeping a separate accumulator copy.

Given that our analysis does not yet realize that this memory doesn't need to be double buffered, this is indeed still an accumulator merging bug causing writes to be spread across several buffers.