Conflicting Port Connections

[mattfel1]

Try MD_Grid. Haven't looked into this at all yet but chisel crashes because of this

[mattfel1]

The problem here is that there is a RegRead that has one instance after unrolling. Specifically, it is used for the start of a counter in a MemReduce. After unrolling, it is also used for the mux that selects between the tree result or the tree result + old value.

The TransientCleanup then decides it needs two copies, one for parent blk -1 and the next for child blk 0. The question is

1. Should it create this second subst rule, or should the read at the parent be allowed to be forwarded to the child? This probably only works if we check for writes to this mem somewhere earlier in the parent's children
2. Is something wrong with the transformer if the first TransientCleanup didn't add this new rule but the second TransientCleanup did?
3. Should the second run of TransientCleanup be allowed to recompute port info as needed?

[mattfel1]

Much easier app to test with:

@spatial class MemReduce1D extends SpatialTest {
  override def runtimeArgs: Args = "1920"
  val tileSize = 64
  val p = 1


  def blockreduce_1d[T:Num](src: Array[T], size: Int): Array[T] = {
    val sizeIn = ArgIn[Int]
    setArg(sizeIn, size)

    val srcFPGA = DRAM[T](sizeIn)
    val dstFPGA = DRAM[T](tileSize)

    setMem(srcFPGA, src)

    Accel {
      val accum = SRAM[T](tileSize)
      MemReduce(accum)(-sizeIn until 0 by tileSize par p){ i  =>
        val tile = SRAM[T](tileSize)
        tile load srcFPGA(i+sizeIn::i+sizeIn+tileSize par 16)
        tile
      }{_+_}
      dstFPGA(0::tileSize par 16) store accum
    }
    getMem(dstFPGA)
  }


  def main(args: Array[String]): Unit = {
    val size = args(0).to[Int]
    val src = Array.tabulate(size){i => i % 256}

    val dst = blockreduce_1d(src, size)

    val tsArr = Array.tabulate(tileSize){i => i % 256}
    val perArr = Array.tabulate(size/tileSize){i => i}
    val gold = tsArr.map{ i => perArr.map{j => src(i+j*tileSize)}.reduce{_+_}}

    printArray(gold, "src:")
    printArray(dst, "dst:")
    assert(gold == dst)
  }
}

[mattfel1]

I put a little patch in BufferRecompute that we should get rid of once we have a real fix for this