Reg Reset Handling

[mattfel1]

If someone writes this:

Foreach(...){i => 
  val r = Reg[Int](5)
  r.reset
  r := ...
  ... := r
}

In old spatial at least, the reset doesn't get handled in the buffer analysis because I added it as dirty as possible. So r would be double buffered and at least in the chisel backend, a reset on a buffered memory wipes all buffers since we can't figure out which buffer to reset. Is it possible to just have resets transform into writes that take the init value of the reg? Or can we have resets be handled correctly in buffering analysis so we can intelligently reset the correct buffer (in the case of RegFiles, overwriting would take too much time)

[dkoeplin]

For registers, reset as a write of the initial value makes sense. For RegFile, yeah you're right, we should handle reset like any other write. It just happens to write the entire memory in one cycle.