nmigen
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m-labs
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
The behavior of a dual port block RAM with read and write ports in different clock domains is not defined during a simultaneous read and write to the same address....
There are a lot of possible combinations of memory ports and many of them are not legal. This depends on the vendor. In this issue we collect such behaviors to...
See https://github.com/m-labs/nmigen/issues/141#issuecomment-509985372 for motivation Todo list (edit as needed to keep up to date): - [ ] fix failing tests - [ ] enable requiring pypy3 to pass in .travis.yml
I've worked around this by putting output buffer instances (OBUFTDS) for all 12 bits in the bus in a single module. It was failing when I used a module per...
Both ports of a SyncFIFO belong to the same control set, which means that the entire FIFO is always reset at once. However, the ports of AsyncFIFO belong to different...
This is solely blocked on Yosys issue yosyshq/yosys#726. It's in my queue for some time, but the threshold for merging it is fairly high (multiple days of randomized testing), so...
The new Atlys platform definition in #15 does the following; ```python Resource("user_led", 0, Pins("U18", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), # LD0 Resource("user_led", 1, Pins("M14", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), # LD1 Resource("user_led", 2, Pins("N14", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),...
``` 17:30 < sb0> whitequark: for multi clock domain designs, I'd also like signals driven in one domain and sampled in another to cause a warning 17:30 < sb0> unless...
This is currently not done because of a quirk (bug?) in Yosys: https://github.com/YosysHQ/yosys/issues/760. This is not right and affects user designs as the `en` signal is a constant and cannot...
Is there any way to write for loops in nmigen or any type of loops
