Generated Verilog should be more readable

[whitequark]

This is solely blocked on Yosys issue yosyshq/yosys#726. It's in my queue for some time, but the threshold for merging it is fairly high (multiple days of randomized testing), so I haven't been able to push it to completion yet.

[mithro]

@whitequark Would having access to a bunch of CPU resources help with the randomized testing?

[whitequark]

@mithro It's kind of a pain to set up VlogHammer in the first place. I think I can use the M-Labs machine for testing that once I have a general confidence in the correctness of the changes to that pass.

[whitequark]

Would having access to a bunch of CPU resources help with the randomized testing?

Actually, what kind of resources can you provide? If it's something monstrous like a 64-core machine I'd be interested. VlogHammer is embarrassingly parallel, so it pays off to use a huge number of slower cores.

[mithro]

I could provide pretty much anything on the list at https://cloud.google.com/compute/docs/machine-types

Anything like the following might work?

• n1-standard-96
• n1-highmem-64
• n1-highcpu-96

[whitequark]

Fixing YosysHQ/yosys#726 proved to be extraordinarily complex, so bumping this from 0.1 milestone.