nmigen
nmigen copied to clipboard
m-labs
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
A number of people have expressed a desire to use nMigen for ASIC design. This issue tracks missing aspects of that workflow. - [x] On FPGAs, asynchronous resets inhibit inference...
I have nmigen code mixed with other RTL language code so am using external simulator. With this option I can now turn off the memory preparation for pysim for all...
It would be nice to have less horrifying build scripts, especially as they increase in complexity due to #251 and similar.
An Array is essentially a mux, and there are several equally valid ways to drive a mux. Currently only straight binary is supported. It would be nice to also have...
Just leaving [this here](https://github.com/RobertBaruch/nmigen-tutorial). Please feel free to point out any errors, inconsistencies, nonsense, or confusing statements.
Investigating #172, it appears that there are two major issues with the way port transparency is handled. 1. Transparent read ports should not be the default, since it is expensive....
This is apparently [a problem](https://github.com/m-labs/nmigen/issues/242#issuecomment-537295898).
This came up on IRC a while back, and I thought I'd write it down for the sake of posterity. Signals should have an optional `must_read` and `must_write` parameter for...
Due to what is arguably a bug in the Xilinx toolchain (since it synthesizes perfectly well-formed behavioral Verilog to something that has different behavior), any `Memory` with an asynchronous read...
Sometimes I want to use generators to build a simulation model of some module. In migen, this wasn't possible for modules that implement combinatorial logic. Trying my hand at nmigen...
