Lucas Bollen

VHDL type / signal naming collisions

1

I encountered a situation where Vivado could not process my HDL because a type "A" collided with a signal name "a". GHC version: 9.0.2 Clash version: 1.6.3 Consider the following...

Vivado does not accept clock names with $ in Verilog

4

Even though ```$``` is an accepted character in Verilog's basic identifiers. Vivado does not accept it in clock names. A constraint file with ```create_clock -name {c$arg} -period 5.000 -waveform {0.000...

Tdp blockram configurations

3

Different configurations for TDP Ram, for each port you can configure the write mode (WriteFirst, ReadFirst or NoChange) and whether or not to use additional output registers. trueDualPortBlockRam takes a...

Clash.Hedgehog.Sized.BitVector.genDefinedBitVector should not use genVec

1

Using `genVec` internally in `genDefinedBitVector` is incredibly slow and should be replaced. I think `Hedgehog.Gen.intergral` would significantly speed up generation..

Can not set initial contents of trueDualPortRAM

1

The `trueDualPortRAM` component (https://hackage.haskell.org/package/clash-prelude-1.6.3/docs/Clash-Explicit-BlockRam.html#v:trueDualPortBlockRam) has no API to set the initial contents like `blockRam` (https://hackage.haskell.org/package/clash-prelude-1.6.3/docs/Clash-Explicit-BlockRam.html#v:blockRam). As far as I know there is no technical reason to not be able to...

Change genDefinedBitVector to use genUnsigned instead of genVec.

1

The current implementation of `Clash.Prelude.Hedgehog.Sized.BitVector.genDefinedBitVector` uses `Clash.Prelude.Hedgehog.Sized.Vector.genVec`. This way of generating `BitVector`s is rather slow. I propose to use `Clash.Prelude.Hedgehog.Sized.Unsigned.genUnsigned` instead as base generator.

Incorrectly using multiple port annotations leads to unexpected error

4

Whenever you accidentally give the some type multiple port annotations, the Template Haskell code incorrectly matches the port types. This reproducer: ```hs {-# OPTIONS_GHC -ddump-splices #-} module Example.Project where import...

Currently the i2c core in the `examples` folder can not be used without copying the files or having a local clone of the reposity. This pull request moves the core...

We currently have functions like `.==.` that can operate on `Signal`s. However, I find myself often writing `.foo. pure bar` when comparing signals to constants. With these changes(inspired by @gergoerdi's...

Derived BitPack instance introduces Dubious primitive instantiation warning

3

The implementation for derived `BitPack` instances produces the following warning when producing HDL: ``` GHC: Setting up GHC took: 0.167s GHC: Compiling and loading modules took: 0.088s Clash: Parsing and...