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Circuit IR Compilers and Tools
When running a design through firtool with `--repl-seq-mem` enabled and `--ir-fir` to emit FIRRTL dialect IR, the resulting file cannot be run through firtool again to get SV output. The...
Hi, I found that using `assert` with dynamic subaccess in firrtl would generate two different type but duplicated `assert` and `$fatal` in verilog. ## Duplicated `assert` and `$fatal` with dynamic...
Consider adding support to exporter for printing out "rawAnnotations" as JSON array on circuit. This would allow better round-tripping of designs containing annotations, and with firtool support to export before...
The following circuit leads to a `firtool` crash: ``` circuit c: module c: wire w: {|a: UInt, b: UInt|} w is invalid ``` The backtrace is the following: ``` all...
The following circuit leads to a `firtool` crash: ``` circuit c: type enum = {|a: const UInt, b: UInt|} module c: ``` The backtrace is the following: ``` :0: error:...
_**Edit:** I initially noticed this behavior using a version of CIRCT that was a few months old but already included the changes from #6138. On commit 649ee55, this fails in...
Mux2if lowering in fitted lowering could create deeply nested regions whose depth is up to 65536. Since mlir is not capable of handling deeply nested regions(there are still recursions for...
In https://github.com/llvm/circt/pull/6582, initial support for classes and objects was added in Dedup. However, this doesn't yet support updating class ports that are ClassType when the classes being referenced in those...
Implement an iterative SCC analysis to compute the forward slice analysis of `FirRegOp`.