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Published 20 hours ago • verified publisher icon llvm

Deeply nested ifs or large mux trees feeding seq.firreg cause exponential behavior.

Open darthscsi opened this issue 1 year ago • 3 comments

darthscsi avatar Jan 23 '24 20:01 darthscsi

Fix dominance in MLIR: https://github.com/llvm/llvm-project/pull/74428

darthscsi avatar Jan 23 '24 20:01 darthscsi

Stack overflow due to recursion https://github.com/llvm/circt/issues/5316

uenoku avatar Jan 24 '24 02:01 uenoku

  • Compile time regression
  • [ ] Replace O(N^2) algorithm with something smarter @prithayan
  • Stack overflow due to recursions against nested regions.
    • MLIR upstream
    • [ ] CSE recursion
    • [ ] wak recursion
    • CIRCT
    • [ ] PrettifyVerilog recursion
    • [ ] PrepareForEmission recursion
    • [ ] ExportVerilog recursion

uenoku avatar Jan 25 '24 16:01 uenoku