[LowerSeqToSV] FIRRTL enum with clock field leads to invalid IR

[mbty]

Edit: I initially noticed this behavior using a version of CIRCT that was a few months old but already included the changes from #6138. On commit 649ee55, this fails in complete silence.

This issue seems related to #6136 and #6138. Did #6138 take enums into account?

Input:

circuit c:
  type t  = {| a: Clock, b: UInt<8> |}
  module c:
    input  in : t
    output out: t
    out <= in

Output (firtool enum_with_clock.fir):

<unknown>:0: error: value has an unsupported verilog type '!seq.clock'
<unknown>:0: error: value has an unsupported verilog type '!seq.clock'
<unknown>:0: error: value has an unsupported verilog type '!seq.clock'
// Generated by CIRCT unknown git version
`ifndef _TYPESCOPE_Enums
`define _TYPESCOPE_Enums
  typedef enum bit [0:0] {enum0_a, enum0_b} enum0;
`endif // _TYPESCOPE_Enums
`ifndef _TYPESCOPE_c__TYPESCOPE_
`define _TYPESCOPE_c__TYPESCOPE_
  typedef
    struct packed {enum bit [0:0] {a, b} tag; union packed { struct packed {<<invalid type '!seq.clock'>> a; logic [8:0] __post_padding_a;} a;logic [7:0] b;} body; }
    t;
`endif // _TYPESCOPE_c__TYPESCOPE_
module c(
  input  struct packed {enum0 tag; union packed { struct packed {<<invalid type '!seq.clock'>> a; logic [8:0] __post_padding_a;} a;logic [7:0] b;} body; } in,
  output struct packed {enum0 tag; union packed { struct packed {<<invalid type '!seq.clock'>> a; logic [8:0] __post_padding_a;} a;logic [7:0] b;} body; } out
);

  assign out = in;
endmodule

[seldridge]

Thanks for the reports on this issue (and the other issues) re: enums. This was never really rolled out to get upstream Chisel use so there are likely a lot of rough edges.