circt
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Circuit IR Compilers and Tools
Now that APInt supports zero width values, we can make hw.constant support them, and expand comb to allow them. Such an approach would make it easier to generate HW dialect,...
It seems that handshake's `LazyFork` violates a required property for composable dataflow circuits: Consider the following example: ```mlir handshake.func @test(%arg0: none) -> (none) { %0:2 = lazy_fork [2] %arg0 :...
Emit functions from the func dialect as regular C functions. This is useful for interop when we, e.g., want to wrap some C++ code in a C function such that...
This PR annotates mux pragmas to memory reads in HWMemSimImpl in a similar way to https://github.com/llvm/circt/pull/3404 ``` /* synopsys infer_mux_override */ assign _GEN_16 = Memory[_GEN_0] /* cadence map_to_mux */; assign...
Input: ```scala circuit Foo: module Foo: input clock: Clock input d: UInt output q: UInt reg _r: UInt, clock _r
More emission patterns.
* Implement emission patterns for all emitc operations except `variable` for which we have our own implementation. Support for template arguments to function calls is not added yet, but can...
The attached MLIR source contains very deep mux trees generated from Chisel which should be re-arranged for better if statement emission. [shim.mlir.zip](https://github.com/llvm/circt/files/9576614/shim.mlir.zip)
Slightly friendlier behavior re:what users expect. Also, handle case when this name conflicts with existing port name (by detecting and generating new name for that module specifically). Update test, add...
