circt
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Circuit IR Compilers and Tools
This commit introduces `seq.hlmem` and ops for providing structural access to the defined memory ports. Please see the updated `RationaleSeq.md` for further info. Edit: still trying to triage the `pure...
This PR lowers the `RefType` of aggregate values, to the `RefType` of the individual elements. A new `RefSubOp` is added to handle the lowering and access individual elements of the...
Following the 21/09/2022 ODM, a consensus was reached on moving forward with supporting zero-width values in the core RTL dialects. If you are aware of any location which currently performs...
Luckily a fairly minor change due to ExportVerilog already have good support for emitting i0-typed expressions as comments. This commit ensures that `hw.array_get` for singleton arrays may be emitted legally,...
(under the assumption that `i0` support for `isHWIntegerType` is merged) emitting `sv.passign` with `i0` wires results in invalid SV: ```mlir hw.module @Top(%arg0: i0, %clk: i1) -> (out: i0) { %0...
This is a followup to https://github.com/llvm/circt/pull/3982 Instead of creating the `CatPrimOp` while iterating over the users of an aggregate value, this commit delays it after all the `Subfield` and `Subindex`...
Add an attribute `preserve_type` to preserve the 1D register generated from `MemToRegOfVec`.
# Issue The following code ```mlir hw.module @m(%a: i8, %b: i8, %clk: i1) -> () { %0 = sv.reg {name = "reg0"} : !hw.inout sv.alwaysff(posedge %clk) { sv.passign %0, %1...
Currently, unwrap operators will create default names for wrap/unwrap ops: ```mlir hw.module @handshake_store_in_ui64_ui32_out_ui32_ui64(%addrIn0: !esi.channel, %dataIn: !esi.channel, %ctrl: !esi.channel) -> (dataToMem: !esi.channel, addrOut0: !esi.channel) { %rawOutput, %valid = esi.unwrap.vr %addrIn0, %2...
# Summary: MWE of loop unrolling + naive store-load forwarding in order to lower nested loops to pipeline dialect. ## Details: This is a really dirty sketch of the hoops...
