circt

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[ExportVerilog] Port types (of lack thereof)

2

`ExportVerilog` leaves off port types (e.g. `input [3:0] a` instead of `input wire [3:0] a`). This ends up producing a ton of warnings in questa (at least). IIRC, there was...

teqdruid

This closes https://github.com/llvm/circt/issues/3001. This PR is a follow-up onto https://github.com/llvm/circt/pull/3015 which didn't consider cases where unary operators appear in the head of subexpression such as `a & b & &a...

uenoku

[FIRRTL] Mega Nit: Double Spaces in FIRRTL Serialized Format

1

This is the biggest of nits, but there are a lot of double spaces (` `) in printed FIRRTL Dialect that always annoy me to see. It would be nice...

seldridge

[ExportVerilog] Reduction Operators Tripping Lint Warnings

1

Consider the following: ```mlir module { hw.module @Foo(%a: i1, %b: i2) -> (c: i1) { %c0_i2 = hw.constant 0 : i2 %0 = comb.icmp ne %b, %c0_i2 : i2 %1...

seldridge

This is obviously not a huge deal, but there is a slight inconvenience in that it appears to be impossible to add new System Verilog tests at the end of...

mikeurbach

[FIRRTL][Verilog] Use Xcelium Coverage Exclusion Magic in Addition to VCS

3

Currently we only emit extracted covers with the VCS magic file-level comment to exclude them: ``` // VCS coverage exclude file ... ``` However, anywhere we emit this, we should...

seldridge

[RFC] [NFC] [FIRRTL] Add a concept of Usages to Grand Central Views

1

Because GrandCentralViews must currently emitted at the same time as the design, it would be nice to emit all possible Views of interest at once and "bucket" them by use,...

mwachs5

[FIRRTL] Add a FIRRTL XMR Op

3

This is a Draft PR, proposing a new `XMROp` and showing its sample usage. 1. Add a FIRRTL XMR Op that lowers to the SV XMR Op. 2. Update the...

prithayan

[StaticLogicToCalyx] Incorrect bound count in dot product.

6

```mlir // Original dot product. // RUN: circt-opt %s -lower-static-logic-to-calyx func.func @main() { %c0_i32 = arith.constant 0 : i32 %lhs = memref.alloc() : memref %rhs = memref.alloc() : memref %result...

cgyurgyik

[PyCDE] Physical Design Code Generators and SystemVerilog Integration

1

While “legacy” integration is easily dismissed as a “detail”, in practice it is anything but. Getting this right gives designers an easy on-boarding path to a particular technology. Getting it...

teqdruid